Технология 90 нм

КМОП 90 LP/RF. Основные параметры

Deliverable ARM library S/C
I/O’s
SRAM
RF’s
ROM
Digital and RF enabled PDK
Base and customer specific IP’s
Features 4 low leakage devices 20 A ZVt
LVt
RVt
HVt
SHVt
52 A DG – 1.8/2.5/3.3 V
ZVt
2 SRAM bitcells (thin cell) 1.18 um2 (single port)
2.2 um2 (dual port)
Dual & Triple Well NFET’s/PFET’s
vPNP, LB & LD matels
MiM 2.1 fF/um2
Capacitor MOS Capacitor
VN Capacitor
Low-k Dielectric
Performance Gatу Delay: 11.2-23.6 ps (LVt - SHVt)
Low Leakage Device options
250 MHz library
Enablement Current PDK on V1500 since Oct 2011 1st Beta Kit Released (V1000) 08/2005
2st Beta Kit Released (V1100) 06/2006
3st Beta Kit Released (V1200) 02/2007
PDK: Digital and RF avaliable
Reference flow: 4Q05 Synopsys
Cadence
Magma
Technology 90FLP
5-10 levels of metal layer 1x, 2x, 4x, analog metal
Wirebond and C4

КМОП 90 LP/RF. Технологические возможности

Standart Features 90 nm lithography
0.10 µm (min)PC linewidth (drawn)
Twin-well on nonepitaxial p-substrate 1-2 Ω-cm
1.2V “Regular-VT” FETs with 21A gate oxide
2.5V FETs with thick (42A)gate oxide
6 to 9 levels of Cu metal + 1 Al level
Parallel-wired center-tapped inductors
Wirebond or solder bump (C4) terminals
Resistor Polysilicon resistor
Diffusion resistor
RF Features RF pcells with RF layouts and RF models for the following devices Regular-VT FETs
Low-VT FETs
1.8V I/O FETs
2.5 I/O FETs
Optional Features 1.8V & 2.5V I/O FETs with 52A gate ox
3.3V I/O FETs with 52A gate ox
1.2V FETs with specific VTs High-VT FETs
Low-VT FETs
Zero-VT NFET thin gate ox
thick gate ox
Triple-well NFETs
MOS Varactors NFET in nwell
thin gate ox
thick gate ox
PFET in pwell
Metal-Insulator-Metal (MIM) cap Nitride
high-k
Vertical Parallel Plate (VN) cap
Precision polysilicon resistor
Silicided polysilicon ballasting resistor
N-well resistor
Vertical PNP (fwd-biased diode)
Electrically Programmable Fuses
Dual Metal option for high-Q inductors